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Summary:

We are looking for an ASIC Top-Level Verification Engineer to join our verification team working on advanced, high-performance ASICs. The role involves verifying complex multi-chip architectures containing processor clusters, DSPs, hardware accelerators, and high-speed interfaces. You will contribute to software-driven verification flows and ensure functional correctness, performance, and reliability across multiple verification platforms.

Responsibilities

• Define and document verification strategies for assigned ASIC components using specifications, requirements, and stakeholder input.
• Develop software-driven tests in C and integrate them into CI-based regression environments.
• Debug RTL designs using industry-standard EDA tools and software debuggers.
• Maintain clean, reliable tests across SystemC/TLM models, RTL simulation, hardware emulation, and silicon.
• Investigate and resolve failing test cases across all verification platforms, including silicon in the lab.
• Participate in cross-team discussions to refine verification methods and improve workflows.
• Contribute to team collaboration, knowledge sharing, and continuous improvement of verification methodologies.

Required Skills & Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Strong C programming skills for ASIC or embedded software environments.
• Practical experience with RTL debugging using SystemVerilog or VHDL.

Preferred Experience in Low-Power Verification

• Hands-on experience with digital power-aware verification flows.
• Ability to build power-verification plans and strategies.
• Setup and execution of power-aware simulation environments.
• Debugging low-power behavior and simulation mismatches.
• Understanding of low-power techniques:
• Clock gating (CG)
• Power gating (PG)
• Multi-voltage domains (MV)
• DVFS
• Memory power modes
• Familiarity with UPF or CPF power-intent formats.
• Experience with power-aware gate-level simulation.
• Exposure to formal verification methods for low-power aspects.

Additional Skills That Are a Plus

• HW/SW co-debugging using SW debuggers for C code running on ASIC hardware (multi-core preferred).
• Experience with XPROP and gate-level simulation (GLS) with timing.
• Debugging on hardware emulators and silicon bring-up environments.
• Simulation and debug experience with SystemC/TLM-based models.